Respect the Silicon…and Bring on the Cloud

Jerome McFarland June 13, 2017 blog, EDA, parallel computing

Putting the “Silicon” back in “Silicon Valley”

In recent years, the software development industry has risen to well-deserved prominence in our social consciousness.  Our interactions with software are ever-present and increasingly crucial to both our personal and professional lives.  As a result, the software industry gets lots of love and attention…with the best software engineers often referred to as “rockstars”.  Even the popular “Silicon Valley” television series, despite its eponymous allusion to the semiconductor industry, is primarily concerned with software. 

Behind the scenes, however, semiconductor vendors continue to quietly toil away, carrying equal weight towards the advancement of technology, delivering game-changing innovations, and impacting every facet of our lives.   Lacking modern integrated circuit (IC) technology, we’d be less safe, less mobile, less connected with one another….and we’d definitely have fewer cool gadgets to play with.

Much like the “silicon” in “Silicon Valley”, semiconductor innovation is hiding in plain sight.  Complex chip designs enable nearly every device that we use…and as the chip designs improve, so do the devices.  For example, the development of smaller, lower-power ICs has enabled mobile devices to get thinner and thinner, while lasting longer.  That, coupled with IC-level integration of various sensor technologies (e.g. MEMS motion sensors, CMOS optical sensors) enables the modern smartphone functionality that many of us have come to reply upon.

Despite its position “behind the scenes”, the semiconductor industry is extremely competitive and increasingly diverse, with a pervasive “innovate or fail” mentality.  Key players in the semiconductor design industry include:

  • Vertically-integrated semiconductor manufacturers – These vendors have captive design and manufacturing resources, typically including their own fabrication facilities (“fabs”) and proprietary semiconductor processing technologies. Vendors making analog and mixed-signal ICs often reside here. 
  • Fabless semiconductor manufacturers – These vendors design and ship chips, but they don’t own their own fabs. The cost and complexity of maintaining and updating fabs has driven an increasing number of vendors into this category.  Vendors who exclusively design digital chips often fall into this category.
  • IP design houses – These vendors design circuits, but don’t ship chips and don’t have fabs. Instead, they sell their IP to semiconductor manufacturers (like those referenced above).

It’s quite common for major design win opportunities (e.g. a lucrative socket in the next big smartphone) to generate fierce, head-to-head competition from vendors in all three categories. 

Time-to-Market vs Technical Risk:  Striking a Delicate Balance

Within their hyper-competitive innovation ecosystem, semiconductor design firms must carefully balance two competing concerns…time-to-market and technical risk. 

In the semiconductor space, as in many others, time-to-market can often make the difference between unqualified success and devastating failure.  The Information Age has broken down the historical barriers to entry (e.g. access to information, tools, and experienced people) leading to a huge influx of global competition.  The number of companies capable of delivering a complex IC design has dramatically increased in the past decade and will only continue to rise.  In parallel, the global appetite for innovation has made semiconductor buyers (e.g. consumer device manufacturers) increasingly willing to consider smaller vendors in the quest to achieve differentiation over their own competition.  These dynamics have led to intense competitive pressure and shorter time-to-market windows…all made more challenging by the trend toward increasingly integrated and complex semiconductor designs.

Unfortunately, the acute time-to-market pressure is in direct opposition with the need to minimize technical risk.  Semiconductor development is a complex, expensive process.  In production, most integrated circuits are created using an intricate photolithography process that requires the creation of expensive photomasks or “mask sets”.  These mask sets often cost millions of dollars when purchased from external foundries.  When you hear of a semiconductor firm racing to “tape out”, it means that they are racing to the stage where the photomask design has been finalized.  In addition to the monetary outlays, each design project consumes the most precious resource the semiconductor vendor has…the time of its design engineers.  Typically, the viability and prioritization of proposed semiconductor projects are evaluated using metrics that explicitly quantify the expected “return on design time”.

As a result, the extreme expense of semiconductor development (both in dollars and opportunity cost) means the impact of mistakes is massive.  It’s a BIG deal to waste precious designer time and an equally BIG deal to spend $$$ reordering mask sets to fix a design error.  This creates an ever-present fanaticism regarding quality and necessitates a rigorous and exhaustive focus on design, simulation, and verification processes to minimize, at every phase, the risk of costly errors.  The ideal semiconductor development result is a rapid “first-pass silicon” success.  Sadly, these are very hard to come by due to the many subtle and complex electrical, chemical, and physical interactions underlying modern chip designs.  In most cases, the need for a second “pass” (a.k.a. a chip revision or “spin”) is baked into IC development timelines…as vendors have reluctantly accepted that post-manufacture testing is likely to expose at least one critical issue that slipped through the upfront quality controls.

More Data, More Problems

At the heart of the challenging “speed vs risk” tradeoff lies the ability to effectively manage and share data.  Expanding design complexity means the associated electronic design automation (EDA) tools need to access more data, potentially distributed across multiple internal teams.  Meanwhile, increasing the robustness of design/simulation/verification checks often means increasing the number of parallel EDA processing jobs run against these expanding data sets.  Finally, time-to-market pressure means that all of this needs to be accomplished more quickly than ever before. 

Simply put…data is a problem. 

However, with sufficiently scalable, high-performance data management solutions, semiconductor vendors could stop compromising when balancing time-to-market with risk minimization.  Effective solutions would enable them to either:

  • Complete a fixed set of EDA analyses more quickly (thus reducing time-to-market)


  • Perform additional EDA analysis within a fixed time window (thus minimizing technical risk)

Capitalizing on the associated strategic advantages will be crucial if individual semiconductor vendors wish to remain competitive.  As a result, semiconductor IT infrastructure is under increasing scrutiny, with data management as a primary focus.

Cloudy Days Ahead

With an intensifying focus on semiconductor IT infrastructure, expanded cloud integration is now a question of “when” and no longer a question of “if”.  The near-infinite scalability of the cloud is a natural fit for the growing data sets that semiconductor vendors need to manage.  Also, the elasticity of the cloud matches well with the sporadic requirements for intensive processing that occur during various phases of the chip design process (e.g. intensive verification before tape out).

Despite these synergies, semiconductor vendors have been slow to embrace cloud integration, due to concerns regarding IP security and EDA tool licensing costs.  The landscape is now changing, however.  Security measures in the public cloud are now far more sophisticated, comprehensive, and up-to-date than the measures that most enterprises can consistently employ on-premises.  Also, tool vendors, such as Cadence®, are now introducing “cloud-ready” EDA platforms with flexible licensing options to facilitate cloud-scale deployments. The evolving cloud ecosystem is now ripe for application to semiconductor EDA workloads.  As a result, the prospect of leveraging cloud-scale compute is catalyzing a strong desire to burst these workloads from on-premises data centers into the cloud for accelerated, massively parallel processing.

Making IT Happen

To fully leverage the benefits of the public cloud, semiconductor IT infrastructure (and specifically, EDA data management infrastructure) must be sufficiently flexible to support the desired hybrid cloud workflows and usage models.  Effective data management solutions must allow semiconductor vendors to:

  • Handle massive, expanding data sets
  • Deliver high-performance data access to accelerate time-sensitive EDA processing jobs
  • Simplify and unify data management across teams, sites, and clouds
  • Eliminate vendor lock-in enabling cost-optimization and choice (i.e. must be HW-agnostic and cloud-agnostic)

Traditional, siloed storage products (e.g. storage arrays, 1st-generation software-defined storage offerings) don’t come close to supporting these requirements.  Instead, the industry now needs fresher, more flexible, approaches to managing data.

At Elastifile, we’ve designed a powerful new solution to address these modern data management requirements, enabling semiconductor companies to strike a more comfortable balance between time-to-market and technical risk.  We call our solution a “cross-cloud data fabric” and we believe it’s just the thing to support the continued evolution of semiconductor IT, both on-premises and in the cloud. 

If that sounds interesting, we’d love to hear from you.

Ultimately, by accelerating and expanding data access and management, we hope to play a small role in ensuring the “silicon” in (both in the real Silicon Valley and around the world) keeps working its magic for years to come.